System Design Verification Validation Test Management Test Cases System Testing

Pnr Jira Perl Python

Bash/csh Perl Tcl Python

C/c++ Python Tcl Perl Shell

Perl Python Gls

System-verilog Python Synopsys Circuit Designer

C/c++ Python Perl Perl and TCL is a plus. Tcl

System Verilog Pli/dpi Interface C/c++ Perl/shell Script

SAP Business ByDesign certific... Finance Sales Procurement

System Verilog C++ Uvm Axi Amba

VHDL Verilog Test bench design Design verification PCB layout

C C++ System Verilog Xcelium UVM

Verilog SystemVerilog UVM

floorplanning clock tree synthesis timing closure signal integrity IR drop analysis

C C++ hardware and firmware design Altium Eagle