Design Verification Engineer

Responsibilities

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

Develop functional tests based on the verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root cause, and resolve functional failures in the design, partnering with the Design team

Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality

Minimum Qualifications

B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science

Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology

Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies

Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications

Experience in the development of UVM based verification environments from scratch

Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs

Experience with revision control systems like Mercurial(Hg), Git or SVN