Design Verification Engineer

General verification expertise –

· System Verilog

· UVM working experience (In the current scenario not much on UVM, but heavily on “C”)

· Understanding of ARM processor based SOCs, AXI / AHB

· Working knowledge of Processor based C tests for SOC verification (test coding, compilation, loading in TB, failure debug)

· Strong hands on work experience of test development, simulation along with usage of popular EDA tools

· Good debug skills –

· Check that engineer has done reasonable amount of debug in past projects

· Has logical and methodical approach to debug issues /failures

· Has used standard tools for debugging, as applicable

· Coresight knowledge / debug is an added advantage.

· We have many tests for connectivity using jasper gold need quick debug effort and it is good have that skill set.

· Good problem solving skills –

· Assess by giving some sample problems to solve online during the interview

· Specific experience with following is a big advantage –

· dynamic cdc verification

· clock sweep tests, dynamic frequency scaling

· verification of complex reset architectures

· Debugging of above issues in GLS environment