Asic Verification Frontend Verification Verification Universal Verification Methodo... Vhdl

C/c++ Python Perl Perl and TCL is a plus. Tcl

ASIC Verilog System Verilog UVM Perl

Application-Specific Integrate... DDR3 SDRAM Functional Verification Perl Python (Programming Language)

Application-Specific Integrate... Computer Simulations System on a Chip (SoC) SystemVerilog Unified Power Format (UPF)

ASIC IP Verification UVM Development AHB/AXI PERL Python

Facebook is the End Client UVM... driver monitor scoreboard agent development System Veri...

Visual Basic Powershell Scripting Citrix Certification Virtualization Vdi Management

Physical Verification Drc Lvs Erc Cadence

Python Perl TCL debugging

Windows Unix Linux SQL Visual Basic

Asic Verification Frontend Verification Verification Universal Verification Methodo... Vhdl

Application-Specific Integrate... FPGA prototyping Field-Programmable Gate Arrays... Formal Verification RTL Design

ASIC Computer Simulations GLS HVL SoC

Soc Verification Uvm/ovm Systemverilog ASIC-SoC Design verification Debugging