Validation Engineer

About the job
Key Skills: SoC verification, UVM/OVM, SystemVerilog, ASIC-SoC Design verification, debugging, randomization constraints, coverage, assertions, problem-solving in AI.

Roles and Responsibilities:

Lead and execute the full SoC verification cycle, from architecture definition to tape-out and bring-up.
Develop and maintain advanced verification environments using methodologies such as UVM and OVM.
Write, debug, and optimize verification test cases for ASIC-SoC designs, ensuring functional correctness and robustness.
Utilize SystemVerilog for constraint randomization, coverage analysis, and assertion-based verification methodologies.
Collaborate closely with cross-functional teams, including architecture, design, and software teams, to achieve project goals.
Debug design and verification issues to support the tape-out and production phases of SoC development.
Implement coverage-driven testing strategies to maximize design validation.
Skills Required:

5+ years of relevant industry experience.
In-depth understanding of SoC design verification processes, from architecture to tape-out.
Hands-on experience with ASIC-SoC design verification and debugging.
Proficiency in SystemVerilog for testbench creation, constraint randomization, and coverage analysis.
Strong knowledge of verification methodologies, including UVM and OVM frameworks.
Excellent problem-solving skills and a passion for taking on technical challenges.
Preferred:

Experience with programming languages such as C/C++ and SystemC (a significant advantage).
Proven success in leading the creation and execution of SoC verification environments for multiple tape-out projects.
Passion for AI technologies and familiarity with AI-driven verification techniques.
Thrives in a dynamic, fast-paced startup environment with a proactive and ownership-driven approach.
Education:

MS in Electrical Engineering, Computer Science, or related field with