Design Verification Engineer

Key Skills: Asic Verification, Frontend Verification, Verification, Universal Verification Methodology, VHDL, System Verilog

Roles and Responsibilities:

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable test benches.
• Work with design teams on test plans, failure debug, coverage, etc.

Skills Required:

• Must-Have:
  • Strong experience in Frontend Verification
  • Hands-on expertise in ASIC Verification
  • Proficiency in Verification methodologies and debugging
• Nice-to-Have:
  • Working knowledge of System Verilog
  • Familiarity with VHDL
  • Experience with UVM (Universal Verification Methodology)

Education: BS, MS in Electrical Engineering, Computer Engineering, or Computer Science