Lan Wan Network Design

System Verilog Uvm

Systemverilog C-based Testbenches Cdc Verification Axi/ahb Uvm

Android Design Agile Git React Native

Axway Design Coding Unit Testing Acceptance Testing

Asic Verification Frontend Verification Verification Universal Verification Methodo... Vhdl

Fixture Design 3d Modelling Solidworks Catia Creo

Single Sign On (sso) Saml/openid Oauth Protocols

Astm Asme Iso Iec Aws

Ams Verilog Systemverilog C

Axure Invision Sketch Miro Adobe Cs

Javascript Angularjs Html5 Css3 Responsive Design

C++ Modern C++ Oops Object-oriented Design Tcp/ip

Snowflake Elt Pipeline Design Sql Scripting Data Modeling Github

Java Spring Boot Azure Rabbitmq Azure Service Bus