Description
Role: Design Verification Engineer (7+ yrs)
Seeking an expert in SystemVerilog, C-based testbenches, and ARM-based SoC verification with strong debugging skills.
Must have hands-on experience with AXI/AHB, UVM, and simulation tools; knowledge of Coresight and JasperGold is a plus.
Preferred experience in CDC verification, dynamic frequency scaling, and reset architecture debugging in GLS.
Strong logical problem-solving and hands-on debug ability are essential
Key Skills
Education
Any Graduate
- Posted On: 15+ Days Ago
- Experience: 7+ years of experience
- Openings: 1
- Category: Senior Design Verification Engineer
- Tenure: Flexible Position