System-verilog Python Synopsys Circuit Designer

C/c++ Python Perl Perl and TCL is a plus. Tcl

Python C++ Verification Engineer

System Verilog Pli/dpi Interface C/c++ Perl/shell Script

CRM software data management tools Database Management Reporting and Analysis Data Verification and Validati...

Validation Engineer CFR ISO Eudralex CFR 820

Agile Methodologies Testing Product Verification Test Development

Linux Tools Python

System Verilog C++ Uvm Axi Amba

VHDL Verilog Test bench design Design verification PCB layout

C C++ System Verilog Xcelium UVM

Switch Lfacs Tirks Leis Nar Wfm

Oligonucleotide Purification Akta systems Unicorn Synthesis

Verilog SystemVerilog UVM

floorplanning clock tree synthesis timing closure signal integrity IR drop analysis