FPGA design Xilinx/Altera RTL synthesis Verilog VHDL

Oligonucleotide Purification Akta systems Unicorn Synthesis

floorplanning clock tree synthesis timing closure signal integrity IR drop analysis

Formality CDC Design Strong analytical System Verilog

Python C/C++ PyTorch TensoFlow Keras

Tcl Perl Python Static Design Checks Synthesis and timing analysis