Description

  • Define electrical verification methodologies for each of the different systems by working with researchers, architects, and the design teams
  • Define and track detailed test plans for the different modules and top-level systems
  • Define, architect, design and drive implementation of scalable test infrastructure
  • Keep track of coverage metrics and bugs encountered and fixed
  • Own execution, interpretation, and reporting of electrical system level verification work status and results
  • Support system bring up and debug activities
  • Clearly communicate test plans and results

Minimum Qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Science or related field
  • 5 to 10 years of experience working as a verification engineer
  • Proficient with UVM and integration verification
  • Strong System Verilog and debugging skills
  • Experience owning areas of product verification
  • Experience with Python and C++

Preferred Qualifications:

  • Master's degree in Electrical Engineering, Computer Science or related field preferred
  • 10+ years of experience working as a verification engineer
  • FAANG background preferred

Key Skills
Education

Bachelor's degree

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