Facebook is the End Client UVM... driver monitor scoreboard agent development System Veri...

Formality CDC Design Strong analytical System Verilog

System Verilog C/c++ Python

C/c++ System Verilog verification Scripting Language Shell Makefile

Linux Scripting C/c++ System Verilog Uvm

C-shell Scripting Verilog-hdl System Verilog Python C

C C++ Assembler Amba Python

C++ OOP System Verilog UVM OVM

VERIFICATION ENGINEER HDL HVL VERILOG SYSTEM VERILOG

Verilog System Verilog Rtl Development Python

Analog Circuit Design Physical design STA Tcl Spectre

System Verilog C++ Uvm Axi Amba

C C++ System Verilog Xcelium UVM

Circuit Design DO-254 RTL Design VHDL Verilog

Perl Tcl C Shell Pytho Systemverilog