Formality CDC Design Strong analytical System Verilog

coding ASIC Tcl Python

CDC ASIC AXI AHB APB

Ddr2 Ddr3 Pcie Spi Srio

Physical Verification Drc Lvs Erc Cadence

Ethernet MPLS ASIC Test Execution Test Planning

ASIC CAD tools Developing Verilog RTL Functional Behavioral Models

C/C++ Ruby Python ASIC Debugging

ASIC design Perl Python Verilog EDA

Python Perl TCL debugging

Synopsys Design Compiler Verplex LEC ASIC design

Fpga C C++ embedded software development Asic

ASIC Verilog System Verilog UVM Perl

CATIA V5/V6 CAD Modeling Microsoft Office Suite ASIC

Application-Specific Integrate... DDR3 SDRAM Functional Verification Perl Python (Programming Language)