C/c++ System Verilog verification Scripting Language Shell Makefile

Design For Test (dft) Scan Insertion Atpg Jtag Bist

Perl Python Tcl Verilog NDM

HardwareDesignDeveloper Verilog SystemVerilog VHDL Scripting

ASIC CAD tools Developing Verilog RTL Functional Behavioral Models

Linux Scripting C/c++ System Verilog Uvm

C-shell Scripting Verilog-hdl System Verilog Python C

C C++ Assembler Amba Python

DDR PCIe Verilog DFM

.NET developer JSON XUnit C# Entity Framework Code

C++ OOP System Verilog UVM OVM

VERIFICATION ENGINEER HDL HVL VERILOG SYSTEM VERILOG

Hardware Validation Verilog LabViEW Python C++

VHDL Verilog Cadence OrCad Xilinx Vivado Altera

SOC Verification Verilog UVM SV