Confluence Jira Git

Uvmsystem VerilogVerificationEngineer Fpga Designs

Data Analysis Data Validation Data Cleansing Data Verification Tableau

Uvm System Verilog C C++ Perl

oftware development projects Designing Algorithms Validation Verification

Python C# Java Windows Linux

Verilog System Verilog C C++ Python

Pnr Jira Perl Python

Software Verification Python Scripts

Software Verification Testing Activities Python Scripts

written verbal communication Problem Solving Arm Logic Verification Debug Infrastructure

Bash/csh Perl Tcl Python

Silicon Verification Engineer

Sdlc Documentation and Reporting Change Management Software Verification and Vali... Configuration Management

Iec Testing Temp Testing Iso 13485 Fda Quality System