Agile Release Train (ART) Scaled Agile Framework (SAFe) Release Train Engineer (RTE)

C++ OOP System Verilog UVM OVM

ASIC design Perl Python Verilog EDA

SystemVerilog Verilog RTL Design Synopsys Cadence

Kernel C / C++ Linux networking RDK

ITK C++ Java AngularJS TC SOA

Agile

Stylesheet customization SOA ITK Agile PLM

Stylesheet customization SOA ITK Agile

requirement document (SRS) Requirement Traceability Matri... and Functional Specification D...

FPGA RTL AMD Xilinx Altera Quartus

ITK SOA C C++ Java/Java Script

Embedded C C++ RTOS QNX Linux

Python Simulink C C++ Matlab

C C++ TCP/IP OpenWRT RDK-B