Circuit Design DO-254 RTL Design VHDL Verilog

Verilog Vhdl Systemverilog Python Perl

Azure Cloud Terraform Powershell Github Omnissa Horizon

Microsoft Word Adobe FrameMaker RESTful API Git version control systems

Scrum Jira Agility/Version One

Data Modeling Version Control Odata Rap Abap

Verilog/rtl Design Perl/tcl Scripting Vlsi

Synopsys Primetime Cadence Tempus Scripting (tcl Perl) Verilog

Scrum Kanban Agile Microsoft Project Visio

Aws Ci/cd Atdd Service Virtualization Version One

Version One Jira Agile Scrum

GPIO UART SPI SW JTAG

Perl Tcl C Shell Pytho Systemverilog

DDR PCIe Verilog DFM

ASIC design Perl Python Verilog EDA