Description

JD:

1. Exposure to Emulation model build and sanity bring up

2. Proven Emulation Test bench bring up experience with C++ and System verilog BFM models is a must

3. Porting C++/System Verilog Simulation Test bench to Emulation expertise is a must

4. Hands on testbench bring up for System verilog, C++ based testbenches

5. BFM coding using C++ or System verilog

6. Strong Python scripting skills

7. Exposure to GPU emulation model build and sanity bring up

8. Good Architecture GPU understanding

9. Strong Functional verification expertise.

10. B. Tech + 12 Years. Mtech + 10 Years (ECE, VLSI)

11. Bachelors or Masters degree in Electronics and communication Engineering

Education

Bachelors or Masters degree