Description

Responsibilities:

Develop Verilog/System Verilog code

Collaborate on transceiver selection and FPGA pinout

Validate features through lab testing and simulation

Document designs and provide technical support

Work with PCB designers, software engineers, and FPGA/ASIC developers

Requirements:

Bachelor’s degree in EE, CE, or CS

6+ years of experience

Expertise in Verilog or VHDL

Strong knowledge of ASIC/FPGA design flow and debug

Proficiency in Vivado or Quartus; familiarity with Xilinx/Intel FPGAs

Experience with 28G+ transceivers and memory interfaces

Knowledge of industry-standard protocols and DSP concepts

Strong teamwork and multitasking skills

Education

Any Graduate