Digital Engineer 3

Essential Job Functions:

Required:

• Bachelor's degree required

• Minimum of 5yrs writing System Verilog and UVM as a primary job function

• Experience with verification of designs written in VHDL

• Experience with Linux command line workflows

• Experience writing TCL to control verification tools

• Demonstrated ability in root-cause analysis of test failures

• Experience working closely with RTL designers to collaboratively resolve verification test failures

• Experience with Git SCM using LFS and Submodules

Desired:

• 10yrs writing SystemVerilog and UVM as a primary job function

• Experience creating prediction models from functional requirements documentation using SystemVerilog or SystemC

• Experience with DPI based simulator interaction for stimulus and prediction

• Proficiency scripting in either Perl or Python for parsing and manipulating text files

• Experience with Questa Sim and Visualizer

• Experience with the UVM-Framework workflow

• Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)

• Experience writing and maintaining Verification Plan Documents

• Experience working on USG Contracts and the associated documentation/process expectations

• Experience with common interface specifications used in spacecraft

• Experience verifying designs targeting radiation hardened Virtex FPGAs