Develop and execute verification strategies for DFX features, including Design for Test (DFT) aspects like Scan, Built-In Self-Test (BIST), and Joint Test Action Group (JTAG) protocols.
Collaborate with design and product engineering teams to deliver manufacturing test patterns and ensure seamless integration of DFX features.
Verify and debug complex systems using Verilog coding skills, conduct gate-level simulations (GLS), and develop patterns for silicon debug.
Preferred Qualifications:
Bachelor's or Master's degree in Electrical Engineering or a related field.
3+ years of practical experience in digital ASIC verification, with a strong understanding of ARM Coresight architecture and implementation.
Proficiency in programming languages such as Verilog, SystemVerilog, Perl, Python, Tcl Scripts, Makefile, and/or C++.
Experience with JTAG IEEE-1149.1 and IJTAG IEEE P1687 standards, and familiarity with tools like Synopsys Verdi for debugging.