Description

About the job

Looking for "DFT Engineers"

Exp level:3+ years

Job Description:

  • Scan insertion.
  • SCAN DRC/Coverage debug.
  • ATPG Pattern generation.
  • Gate level simulations ( Zero delay/Timing Delay simulations).
  • Worked on JTAG/P1500 protocols.
  • Perl/Tcl scripting.
  • Timing/Formal verification/PD flow knowledge is plus.

 

Key Skills
Education

Any Graduate

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