Description

Requirements

  • 7+ years of experience with DFT/DFD/DFM techniques for high-speed processor cores and complex SoC's
  • Well-versed in scan insertion, ATPG, MBIST, JTAG, IO BIST, Scan Compression, and at-speed testing
  • Experience with Tessent or Test Kompress
  • Experience with industry-standard simulation, ATPG, and MBIST tools
  • Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE
  • Experience with scripting languages is a plus
  • Good communication and analytic skills
  • Ability to work with cross-functional teams

Key Skills
Education

Any Graduate

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