Design for Debug (DfD) / Design for Test (DfT) Engineer

About the Role

We are looking for an experienced DfD / DfT Engineer with strong expertise in both Frontend (RTL coding, Architecture) and Backend (Scan Insertion, Manufacturing-related DfD/T). This is a 6-month B2B contract with a possible extension, and the role is fully remote, open to candidates in the UK, France, Netherlands, Sweden, Germany, and Romania.

⚠ Eligibility Requirement: Candidates must be first-priority citizens or have a valid work visa in the mentioned countries, as the role requires export security clearance.

Key Responsibilities

• Lead frontend DfD/T activities, with hands-on expertise in RTL coding and architecture.
• Design and implement DfD/T structures for Program Reset Control, Memory BIST, Clock Control, and similar blocks.
• Drive DfD/T planning and execution for complex SoCs, ensuring high testability and debug capabilities.
• Work on memory repair functionality checks, defining test strategies, and leading a team to execute the plan.
• Handle testability of Analog IPs, developing RTL solutions for SoCs at sub-10nm technology nodes.

Preferred Skills & Experience

• 10+ years of experience in Design for Debug (DfD) / Design for Test (DfT) (15+ years preferred).
• Proven expertise in both frontend and backend DfD/T, with a strong emphasis on RTL coding.
• Hands-on experience with complex SoC design and advanced node technologies (<10nm).
• Knowledge of memory BIST, scan insertion, and analog IP testability.
• Experience in leading teams and driving end-to-end DfD/T implementation.